Exemplary embodiments of the present invention relate to an internal voltage generation circuit and an integrated circuit including the same.
In general, semiconductor devices use an external power source voltage VDD_EX, which is supplied from the outside. Since the external power source voltage VDD_EX may have a change in level due to noise, the semiconductor devices are equipped with an internal voltage generation circuit for generating a stable internal voltage. Here, the internal voltage may include many different types of voltages, e.g., a core voltage VCORE which is used in a core region including a memory cell, a cell plate voltage VCP which is used as a plate voltage of a memory cell capacitor, and a bit line pre-charge voltage VBLP which is used for pre-charging a bit line. Here, the cell plate voltage VCP and the bit line pre-charge voltage VBLP are generated from the core voltage VCORE, and those are generated to have the level corresponding to a half of the core voltage VCORE in order to minimize power consumption. The cell plate voltage VCP and the bit line pre-charge voltage VBLP are generated through the same internal voltage generation unit. Hereafter, an example of the bit line pre-charge voltage VBLP is described.
FIG. 1 is a block diagram illustrating a conventional integrated circuit.
Referring to FIG. 1, the integrated circuit 100 includes a source reference voltage generation unit 110, a core reference voltage generation unit 120, a core voltage generation unit 130, a first internal circuit 140, an over-driving unit 150, a bit line pre-charge voltage generation unit 160, and a second internal circuit 170.
The source reference voltage generation unit 110 generates a source reference voltage VREF. The core reference voltage generation unit 120 generates a core reference voltage VREFC based on the source reference voltage VREF. The core voltage generation unit 130 generates a core voltage VCORE based on the core reference voltage VREFC.
The first internal circuit 140 performs a predetermined operation by receiving the core voltage VCORE. The over-driving unit 150 over-drives a core voltage VCORE terminal in response to an over-drive control signal ODP. The bit line pre-charge voltage generation unit 160 generates a bit line pre-charge voltage VBLP based on the core voltage VCORE. The second internal circuit 170 receives the bit line pre-charge voltage VBLP and performs a predetermined operation.
More specifically, the source reference voltage generation unit 110 generates the source reference voltage VREF based on an external power source voltage VDD_EX (not shown) and an external ground voltage VSS_EX (not shown), and the generated source reference voltage VREF is maintained at a stable level although the conditions of process, voltage and temperature (PVT) may be changed a bit. For example, the source reference voltage generation unit 110 may include a bandgap circuit or a Widlar circuit.
The over-driving unit 150 may operate to secure a fast sensing operation of a bit line sense amplifier (BLSA).
Hereafter, the operation of the integrated circuit 100 having the above structure is described.
The source reference voltage generation unit 110 receives the external power source voltage VDD_EX (not shown) and the external ground voltage VSS_EX (not shown), and generate the source reference voltage VREF. In particular, the source reference voltage generation unit 110 generates a stable source reference voltage VREF although the conditions of process, voltage and temperature (PVT) may be changed a bit.
The core reference voltage generation unit 120 generates the core reference voltage VREFC for generating the core voltage VCORE based on the source reference voltage VREF generated in the source reference voltage generation unit 110, and applies the generated core reference voltage VREFC to the core voltage generation unit 130. Here, the core reference voltage generation unit 120 may generate the core reference voltage VREFC through a down-conversion method.
The core voltage generation unit 130 generates the core voltage VCORE of a predetermined voltage level based on the core reference voltage VREFC and supplies the generated core voltage VCORE to the first internal circuit 140.
Here, the bit line pre-charge voltage generation unit 160 generates the bit line pre-charge voltage VBLP based on the core voltage VCORE and supplies the generated bit line pre-charge voltage VBLP to the second internal circuit 170. The bit line pre-charge voltage generation unit 160 may also generate the bit line pre-charge voltage VBLP through the down-conversion method, just as the core voltage generation unit 130.
Meanwhile, the over-driving unit 150 over-drives the core voltage VCORE terminal in response to the over-drive control signal ODP.
The conventional integrated circuit 100 of the above structure, however, may malfunction as follows.
FIG. 2 is a timing diagram describing the operation of the integrated circuit 100.
Referring to FIG. 2, the core voltage VCORE maintains a predetermined target level by the core voltage generation unit 130, and the bit line pre-charge voltage VBLP maintains a predetermined target level by the bit line pre-charge voltage generation unit 160. In this state, when the over-drive control signal ODP is enabled upon receipt of an active command ACT, the voltage level of the core voltage VCORE terminal is increased while the over-driving unit 150 performs an over-driving operation. The increased core voltage VCORE, however, is used as a reference voltage of the bit line pre-charge voltage generation unit 160. Therefore, the bit line pre-charge voltage VBLP generated in the bit line pre-charge voltage generation unit 160 is also increased during the time that the core voltage VCORE is increased. In this case, the second internal circuit 170 to which the increased bit line pre-charge voltage VBLP is supplied may malfunction.